Field of the Invention
The invention relates to a manufacturing method for a capacitor in an integrated memory circuit.
Capacitors are needed in a number of integrated semiconductor circuits, for example in DRAM circuits or A/D converters. In many cases, the problem arises to realize a high capacitance sufficient for requirements with a minimum space being occupied. That problem is especially severe in DRAM circuits in which each memory cell has a memory capacitor and a selection transistor, while the space available for a memory cell is being continuously reduced. At the same time, the memory capacitors must retain a certain minimum capacitance for reliable storage of the charge and distinguish ability of the information to be read. That minimum capacitance is considered to be 25 fF at the present time.
In order to realize maximum capacitance of the memory capacitor with a given space requirement, among others, trench capacitors are known in which capacitor electrodes are disposed along side walls of a trench located in the substrate.
Another cell concept is the so-called stacked capacitor cell in which the capacitor is disposed as a stacked capacitor above the corresponding selection transistor and mostly also above the bit line. As a result thereof, the entire base area of the cell can be utilized for the capacitor and merely sufficient insulation to the neighboring memory capacitor needs to be ensured. That concept has the advantage of being highly compatible with a logic process.
A memory cell configuration with a stacked capacitor is known from European Patent 0 415 530 B1. The stacked capacitor includes a polysilicon structure with several polysilicon layers disposed essentially parallel on top of one another and connected to one another with a side support. Those layers, which are disposed in the manner of radiator ribs, lead to a significant enlargement of the surface of the polysilicon structure in comparison to the projection of the polysilicon structure onto the substrate surface. The polysilicon structure is formed by alternating deposition of polysilicon layers and selectively etchable silicon oxide or carbon layers on the surface of the substrate, structuring of those layers, producing side coverage (spacers made of polysilicon) on at least one side of the layer structure and selective etching of the silicon oxide or carbon layers. The polysilicon structures are doped with arsenic. Then, a silicon oxide as a capacitor dielectric is formed by thermal oxidation deposited on a cell plate made of doped polysilicon.
Another manufacturing method for such a multilayer stacking capacitor (called a fin-stacked capacitor) is described in European Patent Application EP 0 779 656 A2. A layer structure of alternating p.sup.+ /p.sup.- -doped silicon layers is produced. Each layer structure is divided into two separate partial areas by etching an opening all the way to the underlying substrate and a capacitor is formed from each partial area, which then has a supporting structure on three sides.